1. Field of the Invention
The present invention relates to an electronic circuit and a frequency divider capable of varying and broadening a dividable input frequency band as well as a radio set capable of using two or more radio communication systems by using such electronic circuit and frequency divider.
2. Description of the Related Art
Conventionally, as a frequency divider capable of varying a dividable input frequency band, there is known a frequency divider which is disclosed in the patent reference 1. FIG. 9 is a circuit diagram of a conventional frequency divider disclosed in the patent reference 1.
In FIG. 9, a frequency divider 700 is a half frequency divider which divides an input signal into a signal of a half frequency and outputs the half-frequency signal therefrom. The frequency divider 700 is a master-slave mode D flip flop in which multiplier circuits are connected in two stages.
A master stage 701 comprises: a differential circuit composed of transistors Q1 and Q2; a differential circuit composed of transistors Q3 and Q4; a differential circuit composed of transistors Q9 and Q10; a current source transistor Q13; a load circuit composed of load resistors R1A, R1B and transistor switches Q1A, Q1B; and, a load circuit composed of load resistors R2A, R2B and transistor switches Q2A, Q2B.
A slave stage 702 comprises: a differential circuit composed of transistors Q5 and Q6; a differential circuit composed of transistors Q7 and Q8; a differential circuit composed of transistors Q11 and Q12; a current source transistor Q14; a load circuit composed of load resistors R3A, R3B and transistor switches Q3A, Q3B; and, a load circuit composed of load resistors R4A, R4B and transistor switches Q4A, Q4B.
An input terminal IN is connected to the respective bases of the transistors Q9 and Q12. An input terminal INB is connected to the respective bases of the transistors Q10 and Q11. The output of the master stage 701 is input to the respective bases of the transistors Q5 and Q6 of the slave stage 702.
The output of the slave stage 702 is input not only to the respective bases of transistors Q15 and Q16 but also to the respective bases of the transistors Q1 and Q2 of the master stage 701. An input signal is input to the input terminals IN and INB in the form of a differential signal. The output of the flip flop is obtained from the respective emitters of the transistors Q15 and Q16.
The bases of the current source transistors Q13 and Q14 are respectively connected to a programmable band gap regulator 711. The programmable band gap regulator 711 is able to vary an output potential VREG selectively. This can in turn vary the base potentials of the current source transistors Q13 and Q14, thereby being able to selectively vary a current IBIAS flowing in the master and slave stages.
The transistor switches Q1A, Q2A, Q3A and Q4A are respectively connected to a resistance select signal terminal VA. Also, the transistor switches Q1B, Q2B, Q3B and Q4B are respectively connected to a resistance select signal terminal VB.
According to signals which are input to the resistance select signal terminals VA and VB, the load of the present frequency diver can be switched to the load resistors R1A˜R4A or load resistors R1B˜R4B. When a potential to be applied to the resistance select signal terminal VA is a potential Vcc and a potential to be applied to the resistance select signal terminal VB is 0V, the transistor switches Q1A˜Q4A are respectively turned on and the transistor switches Q1B˜Q4B are respectively turned off. And, as regards the load of the frequency divider, there is obtained a state in which the load resistors R1A˜R4A are selected.
Also, when a potential to be applied to the resistance select signal terminal VA is 0V and a potential to be applied to the resistance select signal terminal VB is the potential Vcc, the transistor switches Q1A˜Q4A are respectively turned off and the transistor switches Q1B˜Q4B are respectively turned on. And, for the load, there is obtained a state in which the load resistors R1B˜R4B are selected. This makes it possible to vary the operation amplitude of the frequency divider selectively.
Based on the foregoing description, the patent reference 1 insists that, due to provision of the structure capable of varying two or more bias currents or the structure capable of varying two or more operation amplitudes, even when using the same chip and same power voltage, the frequency divider is able to vary a dividable frequency band greatly without saturating the circuits thereof.
Patent Reference 1: Specification (Page 3-4, FIG. 1) of Japanese Patent No. 2973858